1. Field of The Invention
The present invention relates generally to a PLL circuit.
2. Description of The Prior Art
Typically, a PLL circuit comprises: a phase comparator for comparing the phase of a reference input clock signal F.sub.ref, which is supplied from the outside, with the phase of an internal clock signal F.sub.vco to output a phase difference signal; a loop filter for receiving the phase difference signal to output a control voltage V.sub.cnt ; and a voltage control oscillator for outputting the internal clock signal synchronized with the reference input clock signal in accordance with the control voltage V.sub.cnt.
In such a conventional PLL circuit, the output (oscillating frequency) F.sub.vco of a voltage control oscillator varies in accordance with the control voltage V.sub.cnt outputted from the loop filter. In order to remedy the irregularity in process for the PLL circuit to enhance the product yield, the variable range (operating frequency range) of the oscillating frequency F.sub.vco, of the voltage control oscillator is desired to be wider. In order to increase the variable range of the oscillating frequency F.sub.cnt, it is required to enhance the gain of the voltage control oscillator. In this case, the variation in the oscillating frequency F.sub.vco to the unit variation in the control voltage V.sub.cnt increases, so that there is a problem in that the frequency variation due to noises increases.